EPP-FSK modem core

Short description of the modem core. If you have the Xilinx tools you can also download the complete modem project. If not, the schematics and vhdl files are available here seperately.
Software version: Xilinx Foundation 1.5i with FPGA Express

Attention: You may not use this design for a commercial product

Disclaimer: If you use any part of this design, I can not take any responsibility for damages you may encounter !

Now for the fun stuff:

Toplevel schematic
Receiver schematic 
Transmitter schematic

VHDL files:

clockdiv.vhd - clock divider in transmitter
descram.vhd - descrambler in receiver
dpll.vhd - clock recovery and DCD detection in receiver
eppctrl.vhd - epp port access
firfilt.vhd - fir output filter in transmitter
hdlcdec.vhd - receiver controller (shift in bits, crc check, ram access)
hdlcenc.vhd - hdlc encoder in transmitter (actually HDLC encoding in done by SW)
nrzienc.vhd - nrzi encoder in transmitter
nrzidec.vhd - nrzi decoder in reciever
ramacc.vhd - control ram access timing
scram.vhd - scrambler in transmitter

Last change: 13.Mar.1999