--===========================================================================-- -- Design units : NRZI encoder -- -- File name : nrzienc.vhd -- -- Purpose : convert from NRZ to NRZI -- -- Note : NON-COMMERCIAL USAGE ONLY -- -- Limitations : -- -- Errors : -- -- Library : -- -- Dependencies : -- -- Author : Juergen Hasch, hasch@t-online.de -- Meisenstr. 23 -- 73066 Uhingen -- Germany -- -- Simulator : Peak VHDL -- Synthesis : Xilinx Foundation 1.4 ------------------------------------------------------------------------------- -- Revision list -- Version Author Date Changes -- 1.0 JH 23 Mar 98 File created -- -- ------------------------------------------------------------------------------- Library ieee; use ieee.std_logic_1164.all; entity nrzienc is port( datain: in std_logic; -- input data stream clock: in std_logic; -- data clock dataout: out std_logic); -- output data stream end nrzienc; architecture behavior of nrzienc is signal q: std_logic; begin process(clock,datain) begin if (clock'event and clock='1') then q <= not(q xor datain); end if; end process; dataout <= q; end behavior; --============================ End of nrzienc ===================================--